The present invention generally relates to semiconductor devices, and more particularly, to a method of fabricating suspended strained silicon for field-effect transistors (FET) and related devices.
Developments in silicon-based integrated circuit technology, including FET technology, have provided greater device speed, increased integration density, and/or improved functionality. However, as transistor dimensions continue to scale-down, a variety of operational and structural problems may arise. For example, as the channel length of a transistor is reduced, short-channel effects such as punch-through, drain induced barrier lowering (DIBL), and increased leakage current may occur.
Alternative transistor designs are being developed to address problems associated with shrinking device dimensions while improving transistor performance. One alternative design involves the use of strained silicon in the channel region of the transistor. Strain may be created in crystalline silicon by applying layers of other materials to physically elongate or compress bonds between the crystal's atoms. For example, germanium atoms may replace some of the silicon atoms near a surface of a silicon wafer, and a thin layer of silicon may be grown on top of this silicon-germanium (SiGe) layer. Because germanium atoms are larger than silicon atoms, the distance between the atoms in the silicon-germanium lattice is greater than it is in pure silicon. As such, when a silicon layer is grown on top of a silicon germanium layer, the silicon atoms may line-up with the silicon-germanium lattice below, which may increase the distance between silicon atoms and thereby create strain in the silicon layer. This strain may enable electrical charges to pass more easily through the silicon lattice. Thus, carrier mobility may be increased in a transistor having a strained silicon channel region.